Theory of electrical characterization of (organic) semiconductors by Peter Stallinga Universidade do Algarve

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Index:

Preface Introduction Device structures Bulk samples, ohmic contacts Schottky barrier    Depletion width    AC: Capacitance       non-uniform doping    DC: Current        space-charge limited current (SCLC)       displacement current    AC: Conductance, Loss, Loss-tangent and Spectra    Deep levels    Interface states    Summary of AC measurements    Admittance spectroscopy, Cole-Cole plots Measuring mobility    Field-Effect Transistor (FET)    Hall measurements    Transient electro luminescence, Time of flight (ToF) Optical effects Time resolved measurements   Emission and capture of carriers   Capacitance-transient spectroscopy      majority traps      minority traps      DLTS   TSC Experimental setup Measurement summary

author:       Peter Stallinga (pjotr@ualg.pt) page location:       http://ceot.ualg.pt/OptoEl/theory/ page last changed:      26 February 2004

Then the next question is: why are some organic materials (polymers) semiconductors? The answer is well described in section IVB of Chapter 2 of "Advances in Synthetic Metals, Twenty years of Progress in Science and Technology" for the basic conducting polymer poly acetylene. In all systems of conductive organic materials, the conducting chain or "backbone" of the molecule consists of unsaturated carbon atoms (example --CH-CH-CH--; each atom is only threefold coordinated). Each carbon atom contributes a single pz-electron to a bond with the neighboring atoms.  This situation is unstable to small symmetry-breaking distortions (so called Jahn-Teller).  In this case an alternating shortening and lengthening of the bonds, or alternating double and single bonds. The band gap that is opened up by this symmetry lowering is in the order of 2.5 eV and this is still in the range of semiconductors. The table gives a comparison of the band gap of various semiconductors. Organic semiconductors mostly fall in the category "wide-band-gap semiconductors".

material  band gap diamond C 5.47 eV GaN 3.36 eV polymer 2.5 eV GaAs 1.42 eV Si 1.12 eV Ge 0.66 eV

With a bandage of 2.5 eV the polymer would not be conducting at all.  This distance between the valence band and conduction band is much too large to allow for free carriers to be generated at room temperature.  For that too happen, an electron would have to acquire huge thermal energy to make the jump to the conduction band. There are still some ways that we can have free carriers in the polymer:

• injection of carriers from metallic electrodes or materials with large amounts of free carriers (for example silicon, or a conducting polymer)
• optical excitation; creation of electron-hole pairs
• doping. The levels of the dopant can be much closer to either band and free electrons or free holes are more easily generated even at low temperatures.

For the theory presented here it doesn't matter what shape the carriers take. We will assume that all carriers are free carriers. One important difference between classical semiconductors and polymers is worth to be pointed out here, though. In classical materials, the conduction is always 3-dimensional, while polymers are 1-dimensional conductors. Or, at least there is an anisotropy; the conduction in one dimension is better than in the other two. Hence, there exist (at least) two processes for conduction with two activation energies. One for conduction along the chain and one for "hopping" to near chains.

In principle we can determine the activation energy for bulk conduction through the measurement of the conductivity as a function of temperature. Normally the resistivity is measured with a four-point probe.  Two points are applying a current and two other points are measuring the voltage.
The resistivity of the sample in the simple model does not depend on the voltage.  In more sophisticated models it does, but they will not be described here.

If we know the parameters of the device we can find the mobility directly from the DC measurements. Otherwise, we have to resort to FETs, Hall measurements, or Time-of-flight measurements, see the chapter on measuring mobility.

For insulating materials, the transport can be of yet another type. In general, it has a stronger field-dependence. Examples:

Fowler-Nordheim tunneling

Poole-Frenkel

A metal and a semiconductor before contact. Note the different Fermi levels which will cause electrons to flow to the semiconductor.	A Schottky barrier formed after contact of the metal and the semiconductor. A region of un- compensated charged acceptors results. This "space charge" causes a voltage drop at the interface.

At equilibrium, in the absence of externally applied voltages, the Fermi level must be constant throughout the sample, since otherwise a current would flow. In the metal the Fermi level is the top of the electron sea, while in the semiconductor, far from the interface, the Fermi level is determined ("pinned") by the impurity level. The Fermi level is matched in the following way: Before equilibrium, the Fermi level is lower in the semiconductor (when the work function of the polymer, E_vac-E_F = c + V_n, is larger than that of the metal, f_m), therefore, electrons will flow from the metal to the polymer. This causes the build up of charges on both sides of the interface, resulting in an electric field and therefore a potential gradient according to Poisson's equation d²V/dx² = r(x).  This is the so-called band bending. In this region, the electric field has caused the holes to move away from the interface; they drift to the top of the valence band. The result is that in this area -- of width W -- there is a surplus of negative charge caused by uncompensated charged acceptors, the "space charge region" or "depletion region", since there is an absence of majority carriers (holes in p-type semiconductors).

The parameters that describe the  Schottky barrier are:

• f_Bp : barrier height. The barrier as seen by (majority) carriers coming from the metal. It depends on the difference in electron affinity of the metal and the semiconductor and (for p-type semiconductors) also depends on the energy gap E_g = E_C - E_V:

                       f_Bp = c + E_g-f_m
It is independent of the position of the Fermi level in the semiconductor and thus on the presence of impurities, etc.
It might be lowered by the so-called image-force-lowering effect which adds to the energy scheme the potential caused by the interaction of the charge with its image (virtual) charge on the metal.
• V_bi : built-in voltage or zero-bias band bending. The barrier as seen by (majority) carriers going into the metal. This is determined by the difference in Fermi level before contact:

        V_bi = (E_vac -E_F)_semicon- (E_vac-E_F)_metal
                             = c + V_n - f_m
• W: depletion width. The width of the area devoid of (majority) carriers. The depletion width can be calculated when the doping profile is known (as will be shown in the next section).

Similar to the Schottky barrier we have a pn-junction (of two equal semiconductors with different doping details) or a hetero-junction (of two different semiconductors).  The theory of these devices is rather similar and will not be mentioned here further.

The Figure shows an example of a system with an acceptor concentration of 4.28 10¹⁵ cm^-3 and a built-in voltage of 0.75 V.

The Figure above shows an algorithm used for calculating depletion widths and capacitances for Schottky barriers ("view image" to see it in more detail).  As an example, consider the situation of a system with two homogeneously distributed acceptor
levels, one 0.1 eV and the other 1.0 eV above the valence band with the Fermi level at E_VB + 0.6 eV. Both have a concentration of 10¹⁶ cm^-3. For e=5, a dot diameter of 2 mm, and a built-in voltage of 0.8 V, the Mott-Schottky plot is given in the Figure.
The Figure shows a simulation of a C^-2V plot of a two-level system as described in the text. For voltages higher than 0.4 V (built-in voltage - E_T1-E_F the band bending is not large enough to put the deepest level below the Fermi level anywhere. Hence the space charge is only a result of the shallow level and we see a large slope (small concentration). For lower voltages, or reverse voltages, both levels contribute to the space charge and both are visible in the slope which is now much smaller. Note that the sharpness of the transition is due to the assumption that around the Fermi level the levels are either completely full or completely empty (emulating 0 K). The situation for T=300 K is shown with a dashed line. Note also that the two slopes do not point to the same built-in voltage V_bi. The slopes will still yield the correct acceptor concentrations, though.

Alternatively, the current can be following the diffusion theory:

Finally, a combination of the two theories, the thermionic emission-diffusion theory predicts a current following the equation

The currents are all of the form

thermionic-emission theory	diffusion theory

From a DC current-voltage plot ("IV plot") we can determine

• the ideality factor n from the slope in forward-bias
• the correct model for conduction
• in thermionic-emission theory the reverse current saturates (levels off)
• in diffusion theory the reverse current depends on the bias
• the saturation current J₀ from the reverse-bias saturation current or the extrapolated-to-zero-volt forward-bias current.
• the barrier height (f_Bp) when the temperature is varied: A plot of ln( J/T ² ) (or ln (JT) for diffusion theory) versus 1/T in strong forward bias (so that "-1" can be neglected) results in a straight line with slope q(V-f_Bp)/k from which the barrier height f_Bp can be derived. Alternatively it can be done in strong reverse bias, so that the exponent can be neglected and the slope will be -qf_Bp/k

                                                        J₀ ~ T ²exp(-qf_Bp/kT )
• The rectification ratio of a device. This depends (for a fixed voltage, say 1 V) on the J₀, also known as "leakage current".

A final note: For high forward voltages, the current may be limited by the resistivity of the bulk. In that case, the current doesn't continue to rise exponentially with the bias, but only grows linearly. In the semi-log IV curves this is visible as a bending of the curve at strong forward bias. Since the current is limited by the bulk conductivity we can again apply the theory for bulk samples.

A special case is when the currents are limited by the space charge. This means that the density of free carriers injected into the active region is larger than the number of acceptor levels. It is easy to see that we then go from situation of band bending caused by uncompensated ionized acceptor levels to the case of band bending caused by over-compensated acceptor levels. The band bending is then in the other direction (!). The local field the carriers feel when injected into the active region is then driving them out of there and back into the contact electrode. The entire current must come from the diffusion of carriers. In other words, the current is caused by the large gradient of density of free carriers. Instead of the simple approximation with only the drift current     I = qmenE we have the more comples form including both the drift current and the diffusion current:     I = qmenE + qDn dn/dx In fact, the drift current is opposing the diffusion current as can be seen in the figure; the electric field will drive the holes back to the metal. In general, we can expect space charge limited currents (SCLC) when the acceptor density is small (and the band-bending and E becomes negative for large amounts of injected carriers) or when the mobility of the carriers is small (so that the first term in the equation above becomes negligible compared to the second term), especially when and where the charge-density gradient dn/dx is large.

The Bell Labs group of Schön and Batlogg gives a nice summary of these measurements (PRB 58), which, in turn, is based on chapter 7.3.4. of Sze . The DC current of a device can be devided into the following types:
In the Ohmic regime, the current is proportional to the electric field. This is equal to a simple resistance.
The space-charge-limited-current regime (SCLC) occurs when the equilibrium charge concentration (before charge injection) is negligible compared to the injected charge concentration. This will form a space charge cloud neaar the injecting electrode; the concetration of the space charge rapidly dies out away from the electrode. In this regime, the current is proportional to the square of the electric field.
With the bias, the trap levels are filled. Above the trap-free voltage limit, the traps are filled and the device enters the trap-free SCLC.
The figure below summarizes this.
 

Ohmic:          J ~ mV Space-Charge Limited Current (SCLC):        J ~ mV 2 Trap-Free Voltage Limit (VTFL):        VTFL ~ d2Nt Trap-Free SCLC:        J ~ mV 2

Note that this is the current through a Schottky barrier. That is, we assume an ohmic contact on one side and a Schottky barrier metal-semiconductor contact on the other side of the semiconductor. If we have two Schottky barriers (for instance because we use the same metal for both electrodes), we get so-called MSM (metal-semiconductor-metal) devices, which have different behavior (notably: the current is proportional to V instead of V ² according to p. 616 of Sze. Not true, see p. 478).

Idisp

=

dQ

=

d(CV)

= C

dV

+ V

dC

= C

dV

+

V

dC

dV

dt

dt

dt

dt

dt

dV

dt

Note that the capacitance of the device also depends on the voltage (see the section on capacitance) and this also contributes to the displacement current. The figure shows an example of a large displacement current compared to the DC conductance. (Sample: PMeT/Al, 2mm electrode diameter, dV=10mV, dt=100ms, T=300K).  The points where the current is zero have moved away from 0 V.  For upward scanning, the displacement current is positive and the situation of zero current is reached earlier, hence the crossing point is at negative voltage.  For the same reason, the zero-crossing point for downward scanning moves to the right. The obvious remedy is lowering the scanning speed.

In general G depends on the applied bias (V_DC) as well as the frequency (w). Later, in the section on admittance spectroscopy we will see why it depends on the frequency. On the other hand, it is easy to show why G depends on the voltage. From the previous section we have

If the level is too deep and the probing frequency is too high compared to the characteristic level filling and emptying times
t, it does not respond anymore.  It is still visible in a certain reduction in the slope in the Mott-Schottky plot, but now without the sudden drop.  Important to note is that the slope is no longer linear and a straight-line fitting does not reveal the true acceptor concentration anymore; the Equation found for the derivative found before is no longer valid.  Also, any extrapolation of the local slope to 1/C²=0 increases to beyond V_bi.

In the presence of a donor level the situation is more complex, since the position of the electron (quasi) Fermi level is not so well known. Its position is determined by the number of free electrons in the conduction band and this depends on many factors such as the mobility, concentration and life time of these minority carriers. What we can say is that the Fermi level moves in the opposite direction compared to the hole (quasi) Fermi level. When the Fermi level doesn't cross the donor level anywhere (this is most often the case, especially for shallow donor levels), the donors just act as compensation for the acceptors and a reduced acceptor concentration is found in the plots, N_A -N_D.

The Figure shows two simulations. In both simulations there are two levels (one shallow and one deep). In the first simulation the deep level is responding (dotted line), while in the second it is non-responding (solid line). The parameters for the simulations are given in the Table.

As for the frequency response, we can say the following: For very low frequencies the deep states have adequate time to reach thermal equilibrium at all moments and the amount of charge transferred is proportional to the number of deep levels and is independent of the frequency. When the frequency is increased beyond the relaxation time of the levels (see section on emission and capture of carriers) the amount of charge transferred is diminished, simply because the levels have no time to reach thermal equilibrium. We will measure a much reduced capacitance and conductance. To summarize: for deep levels we expect a bend or a drop in the CV plots and a peak in the loss-tangent (tand = G/wC) occurs when the radial frequency w is equal to the reciprocal relaxation time 1/t.

At forward bias, the Fermi level is under the interface states and they are therefore empty (contain no electrons). When the bias is lowered, there comes a moment where the Fermi level is resonant with the interface states and they are partly filled. In that case, when the Fermi level is modulated (by the external bias) charge will flow into and out of the interface (states). This is equivalent to a capacitance.  Because energy is lost in the process of moving the charges, part of the current is in-phase with the external voltage and is therefore observed as conductance. When the bias is further reduced, the Fermi level is completely above the interface states and modulating it will have no effect on the amount of charge present there; no current will exist that is associated with the movement of charge. We can therefore expect a peak in the capacitance-voltage  (CV) as well as a peak in conductance-voltage (GV), see the figure below.
 

C-2-V plot (left) and Log(G)-V plots (right) when interface states are present

To summarize: for interface states we expect a peaked response in the CV and GV plots and flat Cw and Gw plots up to a certain frequency from where they will fall off rapidly. A maximum in loss-tangent (tand = G/wC) occurs when the radial frequency w is equal to the reciprocal relaxation time 1/t.
 

continous band of states

model	C-2-V plot	Log(G)-V plot	spectra C, G/w        and           tand
E: single shallow level x: homogeneous	straight line	straight line	"flat" (1/w)
E: + deep levels x: homogeneous	+ bend or drop	straight line	peak
E: + deep levels x: interface (or local)    states	+ peak	peak	peak (only at certain voltages)
E: + deep levels,    homogeneously  distributed x: interface (or local)    states	peak (pos. depending on ac frequency)	peak (pos. depending on ac frequency)	peak (pos. depending on bias)

 Very often, the data can be described very well with equivalent circuits. The advantage of them is that a lot of things can be described in this way, but the disadvantage is that the physical meaning of the found parameters is often difficult to interpret. One example of an equivalent circuit that is very illustrative and that still has a strong link with the actual physical structure of the device is the following:
 

In the picture on the left the device is thought of as consisting of a bulk part (denoted with b) with its capacitance and resistance placed in series with the interface part (denoted with d).

This seems a very reasonable assumption. Even in such a simple circuit, the measured capacitance and conductance follow complicated equations. Even if we take the elements in the circuit to be frequency independent, the measured values are not. Some calculations can show that
 

C  =	Rd2Cd + Rb2Cb + w2Rd2Rb2CdCb(Cd+Cb)
	(Rd+Rb)2 + w2Rd2Rb2(Cd+Cb)2

G  =	Rd + Rb + w2RdRb(RdCd2+RbCb2)
	(Rd+Rb)2 + w2Rd2Rb2(Cd+Cb)2

Under the approximations R_b << R_d and wR_bR_dC_d² >> 1 the loss tangent reduces to

tand  =	wCdRb
	1 + (wRb)2(Cd+Cb)Cb

Some people prefer to present the admittance data in the form of so-called Cole-Cole plots. In that case we plot the loss versus the capacitance. The figure shows an example. For systems as described above it can be shown that the plot is a semicircle (with the center on the horizontal axis) and meeting the horizontal axis at C=Cgeo and C=Cd. If we know the dimensions of the device, A and d, we can calculate the permittivity e of the material: e = dCgeo/A

In the figures of the loss-tangent we see a local maximum somewhere at a frequency

wmax  =
	1		1
	Rb		Cb(Cb+Cd)

This gives a handle for the measurement of the activation energy of the bulk conductance. When the temperature is changed, the bulk resistance changes and - assuming that the capacitances are relatively independent of temperature - the position of w_max should follow the bulk resistance. With the assumption that the bulk conductance is singly activated, the resulting temperature dependence of w_max is

In the above theory, all parameters are assumed constants. This is not a correct picture. For instance, the capacitance of the depletion layer C_dis temperature and frequency dependent. A distribution of levels in energy will cause a frequency dependent capacitance of the form
 

Cd = C0		1 -	kT	log		1 + w2t02 exp[ 2 (EV - EF + qVS)/ kT]
			2qVS			1 + w2t02 exp[ 2 (EV - EF)/ kT]

For w=0 C_d reaches the low frequency value C₀ (which is still voltage dependent), while for infinite frequencies the capacitance drops to zero. For deep levels, with t very slow, the most visible result is that the capacitance doesn't flatten out at lower frequencies. Otherwise not much changes. The position of the maximum of the loss tangent, for instance, is rather invariant to such effects.

The Figures show a simulation with the same parameters as before but now with a frequency dependent capacitance. Note the non-saturating capacitance at lower frequencies.
Some remarks:

• The equivalent circuit can be expanded with other RC loops. For instance, an extra RC loop can be added to simulate that the material has two parts with different doping densities (see  Forero et al., 1999 ). Every loop causes a peak in the loss-tangent and an extra semi-circle in the Cole-Cole plots. Therefore, if we have n loops, we will have n-1 semicircles and n-1 peaks in the loss-tangent.

Also loops can be added that do not directly have a link to the geometrical nature of the device. In principle any process that has a relaxation time t can be simulated with a loop, such that t = RC. For example the relaxation process from the interface states as described in the previous section. Via the temperature dependence of the peak in the loss tangent, and hence of the time constant t, the activation energy of this process can be measured. The physical meaning of the equivalent circuit is then lost, but the electronic engineer still likes to model the device in circuits.

	symbol meaning L channel length Z channel width d oxide thickness VG gate voltage VD drain voltage (VS=0) ID drain current m (hole) mobility
MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. In this case the metal is replaced by low-resistive silicon.  The current from source (S) to drain (D) is controlled by the gate (G) voltage

The saturation current follows the equation

Here is an example: The picture on the right shows the IV plots (I_D vs. V_SD) of an FET for various gate-source voltages (V_S=0), ranging from 0 V (top) to -35 V (bottom) in steps of 5 V. With a source (and drain) electrode length of 25 cm and distance of 25 mm and oxide thickness of 800 nm the mobility of the holes can be calculated to be 3 10^-6 cm²/Vs.

Effects that we have to be aware of are
Velocity saturation. For high fields, the velocity of the carriers is not proportional to the field, but instead saturates to a certain value. This makes that the saturation current (I_ds for V_ds > V_gs-V_t) depends linearly on the gate voltage rather than quadratic (see p. 450 of Sze, )
Contact resistance. If we ignore the contact (or series) resistance at the electrodes of the device, we can underestimate the mobility, see Horowitz et al, JAP 1999).
Short-channel effects. These occur when the inter-electrode distance becomes comparable to the depletion layer widths. In this case, all sorts of deviations from standard theory can occur, see section 8.4 of Sze .
Other non-linear effects can make the mobility (gate) voltage dependent. In most cases the mobility drops for increased gate-voltage (Fig. 8.13 of Sze, ), but also the opposite can happen (Vissenberg, PRB 1998, ).

A good starting point for measuring organic FETs is the article of Horowitz, "Organic Field-Effect Transistors" .

When we take a bar of semiconductor without any rectifying contacts we can measure its resistivity r, or conductivity s=1/r which can be expressed in terms of mobility and free-carrier density:

mp	=	lxVy
		BzVxWy

This method is probably the most direct way of measuring the velocity and hence the mobility of the carriers. With an electric pulse, electrons and holes are injected from opposite sides into the active layer. When the carriers meet, somewhere in the active layer, they will recombine and produce light. The time delay (Dt) to the onset of luminescence directly gives you the speed of the fastest carriers (in most organic materials these are holes), assuming you know the thickness of the layer (d) through which the carriers must travel m = v/E = (d/Dt) / (V/d) = d2 / VDt

This method is similar to time resolved electroluminescence, but instead of measuring the light we measure the time-resolved current on the other side of the voltage or light pulse. The results are the same.

Light emitting diode:
Under forward bias, majority carriers (holes from the polymer and electrons from the metal) are injected into the depletion region. As the name implies, and as we have seen in the beginning of this document, in thermal equilibrium density of free carriers in this region is very low.  The injected carriers will therefore try to recombine in a constant way restoring equilibrium. The energy that is released in the process is carried of in the form of photons, which, if they are not reabsorbed in the material can be detected externally.
The energy of the photons, and hence their wavelength (read color) is determined by the difference in energy between the holes and the electrons. Holes are mostly available in the top of the valence band and electrons in the bottom of the conduction band. This energy difference is therefore equal to the bandgap. For classical semiconductors (e.g. Si) this energy is in the range of infra-red.  For wide bandgap semiconductors (such as GaN and most polymers) the bandgap is in the order of 2.5 eV and this implies that the photons are in the blue part of the spectrum. A decade ago, the existence of blue LEDs was still a thing of the future and research was focused on finding a suitable material. Candidates included SiC, GaN, ZnSe, etc.
In the ideal case, all injected electrons recombine with all injected holes (somewhere in the middle of the depletion region) and the quantum efficiency is then 1, namely one photon emitted for every electron-hole pair injected.

It has to be noted that for an LED it is not necessary that there exists a rectifying contact. The only prerequisite is a region of low equilibrium-free-carrier concentration into which free carriers are injected.  In fact, most polymer LEDs are made of ultra-pure (and hence highly depleted) semiconductor material sandwiched between two metals (often transparent ITO, indium-tin oxide) which act as electron injectors (cathodes) and hole injectors (anodes).  Because there is no space charge inside the polymer there exists a linear voltage drop, instead of the quadratic voltage drop of Schottky barriers, see the figures below.

There are two ways the light efficiency might be impaired:

1. Unbalanced carriers. If only one of the types of free carriers are injected into the depletion region, there is obviously no recombination.  In that case, the excess energy is carried off in the form of heat.
2. Non-radiative recombination. If there exist recombination paths without the emission of photons, the light efficiency can also be reduced. Many defects are non-radiative recombination centers. In a way, defects are needed to provide the material with free carriers in the neutral regions, but in another way, defects are unwanted because they can reduce the luminescent efficiency. On the other hand, for fast, non-optical electronics, recombination centers are needed

Photo-detector / solar cell:

In a photo-detector or solar cell, the opposite process takes place.  The energy of photons is used in producing electron-hole pairs which are subsequently broken up by the strong electrical field in the interface. These free carriers arrive at the electrodes where they contribute to an external current. In this case, it is also not really necessary that there exists a rectifying contact. The only prerequisite is a strong electric field at the place where the electron-hole pair are formed. This field should be stronger than the binding energy of the e-h pair. At Schottky barriers such fields are easily present because the voltage drop occors over a very small length, but at sandwich structures large external voltages are needed. Moreover, no short-circuit currents are possible; The moment we short-circuit the device, the field is (nearly) gone and carriers are not separated or transported to the electrodes. Thus, while the sandwich structures are still good for photodetectors, they are not suitable for solar cells.

The parameters that characterize a solar cell are

• the open-circuit voltage (V_oc). This is the voltage when no current is running and in the IV-plot this is the voltage where the IV curve intersects the voltage axis.
• the short-circuit current (J_sc). This is the current when no voltage exists across the device and in the IV-plot this is the current where the IV curve intersects the current axis.

The figures show the IV curves in the dark (black) and under illumination (red) in logarithmic scale and in linear scale.
 

The Figure shows the processes of capture and emission of holes from a deep acceptor level at E_T with density N_T. The number n_T stands for the number of levels filled (with holes). The rest of the holes, N_T-n_T, must then be in the valence band (in this simple model which neglects a contribution of the intrinsic holes originating from the conduction band). The other numbers, e_p and c_p stand for the emission and capture rates (in units number-per-second-per-available-hole). The number of holes actually being emitted and captured is then proportional to these values and the number of available holes in the states: c_p(N_T-n_T) holes per second will be captured onto the trap and e_pn_T will be emitted per second. In equilibrium there is no net transfer of holes. This requires

As seen above, the ratio of emission and capture depends on the Fermi level. We now make the assumption that the emission of holes from a trap level to the valence band is a property of the trap¹. The capture of holes from the valence band is proportional to 1: the capture cross-section, s_p. 2: the number of free holes in the valence band, p. 3: the average thermal velocity of these free holes, <v_p>.  In Equation 1:

1: we make here the assumption that the number of available "destination" states is infinite so that is not causing a bottleneck in the emission process

In DLTS (deep level transient spectroscopy) the capacitance is monitored over time after a sudden change of bias. The above figures clarify what happens to the capacitance after a switch of bias. Easiest is it to understand if we remember that the capacitance is directly linked to the depletion width:

r(x)d²x = V_bb

When the voltage is switched to reverse bias many things will happen. A different voltage drop V_bb occurs at the interface. This implies a new depletion width and a new capacitance according to the above equations. The new equilibrium capacitance takes time to reach. The following things will happen:

• 1: The free carriers (holes in the valence band) will rapidly move out of the interface region. The space charge increases.
• 2: A new, larger, depletion width is reached.
• Larger depletion width means smaller capacitance.
• Inside the new depletion width the deep level, which cannot respond so fast, is off equilibrium close to the interface.
• 3: Charges (holes) are slowly emitted from the deep level to the valence band at a time scale t. These charges are immediately swept away by the electric field.
• Because the space charge density increases closer to the interface, less depletion width is needed. (Visualize: the integration of Poisson's Equation reaches V_bb a little earlier). W shrinks.
• If W shrinks, C increases. This then happens at a time scale of the hole emission life time t.

To find the trap activation energy, E_pa, we can use the equation for the emission rate e_p (=1/t) found in the section Emission and capture of carriers. e_p  = gT²s_pa exp(-E_pa/kT). If we monitor the characteristic decay times of the transients as a function of temperature and plot this in the form ln(tT ²) vs. 1000/T, the resulting straight line will yield the activation energy.

Note: to truly measure the capacitance of the interface, C_d, we must chose a frequency low enough to be below the cut-off frequency of the bulk, see the section on admittance spectroscopy. For higher frequencies we would measure only the bulk properties, which have no transient effects.

When the voltage is switched to reverse bias, the following things happen (the differences for minority carrier traps are indicated in a bold font):

• 1: The free carriers (holes in the valence band) will rapidly move out of the interface region. The space charge increases.
• 2: A new, larger, depletion width is reached.
• Larger depletion width means smaller capacitance.
• Inside the new depletion width the deep level, which cannot respond so fast, is off equilibrium close to the interface.
• 3: Charges (electrons) are slowly emitted from the deep level to the conduction band at a time scale t. These charges are immediately swept away by the electric field.
• Because the space charge density decreases closer to the interface, more depletion width is needed. (Visualize: the integration of Poisson's Equation reaches V_bb a little later). W increases.
• If W increases, C decreases. This then happens at a time scale of the hole emission life time t.

To summarize: after a switch of the voltage to reverse bias we first observe an immediate decrease of the capacitance (1) and after that a slow further decrease of the capacitance at time scale t (3). This is very similar to majority carrier traps, but the sign of the transient is reversed; DC is positive here. We can still determine the trap activation energy by monitoring the characteristic transient decay time t as a function of temperature.

Basic principles
How DLTS works is the following. Capacitance-transients are recorded in the same way as described above. The device is placed in the emptying voltage V_E and the system is allowed to reach thermal equilibrium. For a short time the device is placed under the filling voltage V_F. In this times the traps will fill with charges. When the voltage is switched back to V_E a transient is observed as described in the previous sections. From this transient two samples are taken at times t₁ and t₂ after switching the bias. The DLTS spectrum is now the difference in capacitance at these two times as a function of temperature:

This means (substituting the explicit form of the transient, see the section on capacitance-transient spectroscopy)

The explicit temperature dependence of t is (see section on emission rates)

Parameters of DLTS are:

• Repetition rate: how many times per second a transient is recorded. The time between two transients should be long enough to ensure that the system is in thermal equilibrium.
• Time window: The values of the sampling-point times t₁ and t₂.
• Filling voltage V_F and emptying voltage V_E.
• Filling time: how long the device is placed in the filling voltage V_F before switching back to reverse voltage V_E.

Capacitance transients at several temperatures	Resulting DLTS signal for majority traps (down)  and minority traps (up)

Example
The Figures show a simulation of DLTS. The left figure shows simulations of transients caused by a 0.2 eV deep majority carrier trap for various temperatures (44 K to 52 K in 2 K steps). For the lowest temperatures the transients are very slow (bottom trace) and the difference between the capacitance at t₁ and at t₂ is small, hence the DLTS signal S(T) is very small. When the temperature is increased the transients become faster and the DLTS signal increases. Note that the signal has negative sign; for majority carrier traps, the transient has an upward trend and therefore C(t₁) is smaller than C(t₂). When the temperature is further increased, the transients become so fast that they already died out before the time window (t₁-t₂) and the DLTS signal has vanished again. The figure on the right summarizes this for the majority carrier trap (red dots; lower trace). In the same figure a comparison is given with a minority carrier trap (blue dots; upper trace) whose DLTS signal has the opposite sign because the related transients have downward trends. Also, in this simulation the minority-carrier trap is chosen to be a little more shallow (0.16 eV). Assuming that the pre-factor t₀ is identical (1.3 10^-18 s in both cases) it means that the peak has shifted towards lower temperatures.

Comments
The advantage of this scheme is that it can be done completely automatically with a minimum of data processing. The disadvantage is that of the entire transient only two points are used; most of the data are thrown away and the duty cycle of the measurement is very low. In Laplace DLTS the duty cycle is much higher because the entire transient is used in a Laplace transformation. The cost is a more elaborate calculation; only modern computers can be used.
In reality, DLTS is more often used not to determine the trap activation energies but more to show the presence of certain impurities through their fingerprint spectra and to determine their densities through the intensity of the DLTS spectra and through the underlying amplitude of the transients. This is based on the fact that the amplitude of the transient is linearly proportional to the density of the deep defect relative to the density of the dopant (assuming that this ratio is small).

1: To be precise, the word spectroscopy is misplaced, because in a spectroscopy experiment an experimental value is monitored while the frequency is scanned; a spectrum is the visualization of an observable as a function of frequency. In DLTS no frequency is scanned, so the name is slightly inadequate. In DLTS (normally) the temperature is scanned and the DLTS-signal intensity is plotted. The end plot resembles a spectrum in that it shows peaks and that it is a "fingerprint" of the defect in the material. It would have been better if "scanning" was used for the S in the acronym DLTS.

From TSC, the activation energy of the trap can be determined in the following way (p-type material):
In the depletion zone, there are no free carriers and the capture of carriers does not take place. Holes are emitted from the traps at a rate e_p and the number of filled traps n_t therefore changes with a speed

The activation energy can also be found directly from a single TSC scan. A peak in a TSC scan follows the equation

I  =	A exp(-Q)
	[ 1 + B exp(-Q)Q-2 ]2

In either case, the integrated current over time reveals the number of defects emptying their charge and this can then be related to the defect density if we know the dimensions (depletion width W ^*and electrode area A) of the active region.

NA = (1/eWA)

I dt

The figure shows an example of a TSC measurement with parameters: Ea = 0.5318 eV,  A = -0.269 A, B = 9.49 1012 (b=1x), 4.74 1012 (b=2x), 2.37 1012 (b=4x). Note that the integrated curve (over time!) is equal in all three cases. The biggest curve looks larger, but it is scanned at higher speed.   I dt   =  I dT dt/dT    =   (1/b) I dT

• Power supply: to be able to apply a bias voltage to the device
• (Pico)ampere meter: to be able to measure the current through the device
• RCL (resistance-capacitance-inductance) bridge: to measure the capacitance and the conductance (loss) of the device
• Temperature controller: to stabilize or scan the temperature (for instance in DLTS studies)
• Optical equipment: for optical transients, or optical spectroscopy (not discussed here)
• Computer: for steered data acquisition

	Setup for DC conductance (G) measurements. Setup for current transient  measurements.
	Setup for AC measurements of conductance (G), loss (G/w) and capacitance (C) Setup for capacitance transient measurements and DLTS

How does the RCL bridge work? In most cases it works like a lock-in detector that monitors the current when an AC voltage it applied to the device. All the current that is in phase with the voltage is interpreted as conductance (G=1/R) and the current that is out-of-phase is linked to the capacitance. This is based on the properties of resistors and capacitors, I_R = V/R (Ohms law) and I_C = C dV/dt. When a sine-wave voltage V_in is applied to the device, the currents for the capacitor and resistor can be calculated:

From this, the conductance can be calculated as G = I₀/V and the capacitance as C = I₉₀/wV, with I₀ the amplitude of the in-phase current and I₉₀ the amplitude of the out-of-phase current. Here we made use of the fact that sin and cos are 90 degrees out of phase. Now the trick is how to decompose the current into the in-phase current and the out-of-phase current parts. For this we can make use of a lock-in detector (a.k.a. "phase-sensitive detector"). What happens is the following:
 

The signal S (proportional to the current I) is multiplied by a square wave signal with the same period as Vin, the so-called reference signal Vref. When the phase of this reference is equal to the phase of the signal S, the result is a rectification of the signal (see the Figure). After rectification, the signal is put through a low-pass filter (RC-filter). The result is a DC signal whose amplitude is proportional to the amplitude of that part of the input signal S that was in-phase with the reference. If the starting signal was out of phase with the reference, the result would have been zero after the RC-filter, see the right part of the Figure. The output signal is proportional to the conductance only. In this way, simultaneously, two channels are used. One channel with the reference signal in phase with the applied voltage Vin and one channel with the reference 90 degrees out of phase. The first will monitor the conductance and the latter will monitor the capacitance.

	device structure	shallow level position	shallow level density	deep level position	deep level density	free carrier mobility	conduc- tion model	interface states	difficulty / cost
IV	Schottky/pn bulk								1
CV	Schottky/pn								3
admittance spectroscopy	Schottky/pn								4
IV	FET								2
Hall	bulk								8
TSC	Schottky/pn								3
DLTS	Schottky/pn								5
ToF	bulk								8

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