To explain how a field-effect transistor works, we start with a
MOS-FET (metal-oxide-semiconductor field-effect transistor) or a
MIS-FET when the insultaor is not silicon-oxide. As we will see,
can be well described by a MIS-diode with source and drain
in the plain of the active layer. Therefore, it is best to start
MIS juntion. Then we can extend this theory to finally arrive at
::: MIS junction.
::: Capacitance of an MIS junction
::: Field-Effect transistor (inversion channel)
-- Linear region
-- Threshold voltage of an inversion-channel FET
-- Subthreshold region of an inversion-channel FET
-- Contact resistance
-- Other contact effects
::: Organic FETs
-- Accumulation-channel FET
To understand how an FET (of the MOSFET type) works, we first have to analyze what an MIS structure is.
In a simple approximation, a MOSFET is a planar device of semiconducting material whose free carrier concentration n, and hence it conductivity (via g = men) is controlled by the gate.
The first figure shows an energy diagram of an MIS device. The
consists of a metal and a semiconductor separated by an insulator.
we assume that the insulator is not conducting any current.
Standard textbooks start with an ideal MIS device, which means that the Fermi levels in the metal and the semiconductor are aligned even before contact. In other words, the work functions of the metal and of the semiconductor are equal, fm = c + EC-EF. This implies that we have no band bending in the absence of external voltages. Remember the Schottky barrier, where charge was flowing from one side to the other due to the misalignement of the Fermi levels. In the ideal MIS junction such a flow of charge is not needed (which saves us the trouble of explaining how it can pass through the oxide :-)
|fm : the
How much it costs to take an electron from the top of the
in the metal to vacuum. The "workfunction" of the
semiconductor can be
defined as c + EC-EF.
fb : (not shown, beause it doesn't enter into the calculations): the barrier height of the oxide as seen from the metal; the difference between the "conduction band" of the oxide and the Fermi level of the metal..
c : the electron affinity of the semiconductor. The energy it takes to take an electron from the conduction band to the vacuum level.
EG : energy gap of the semiconductor.
YB : the energy from the midgap level to the Fermi level. This is approximately equal to EG /2
EC : bottom of conduction band.
EV : top of valence band.
|The following strip explains what happens when we
voltage to the metal (gate). For that we use the legenda
as shown here
on the right.
Note that the (horizontal) SCALE of the pictures is changing. Just like in Schottky barriers, the depletion width depends on the voltage. Here the depletion width is shown as constant.
When a small (positive) voltage is connected to the metal (gate), free holes are pushed out of the interface region and a band bending results on the other side of the insulator. This is the same effect as seen in a Schottky barrier. Free carriers (holes) flow out of the interface region and a depletion zone is formed. The uncompensated (negatively) ionized acceptors cause an electric field and - via Poissons equation - a parabolic bending of the bands.
Note that there is also a voltage drop in the oxide. In the oxide no charges can reside and hence the field is constant and the voltage drop is linear in space. The total voltage drop in the oxide plus the band bending is equal to the external voltage.
When the voltage is further increased, at the interface an inversion region is created. The semiconductor becomes here n-type, albeit not very conductive, yet.
c) Strong Inversion
For very strong bias, the Fermi level crosses the conduction band close to the interface. This is strong inversion. Free electrons are in a so-called "channel" next to the oxide. This channel is therefore highly conductive.
The ample availability of states in the conduction band means that further increases in the gate voltage will not extend this strong inversion region into space, but rather will increase the density of electrons in the channels. The channel is always infinitisimally thin.The huge amounts of free carriers can easily cause a large voltage drop (band bending) and only a thin layer is needed to "absorb" the external voltage.
Note that the depletion width (the white zone) and the inversion width (lightblue zone) are constant once the channel is formed.
Going in the other direction, a negative voltage at the gate metal will attract some free holes to the interface. In this accumulation region, an increased number of free holes is created, although it is not yet dramatic; the interface is still high-ohmic.
e) Strong accumulation
For stronger negative voltages at the gate the Fermi level is forced below the valence band at the interface. A channel with high density free holes is created. This is called strong acummulation.
Again, as for the strong inversion case, further increasing the voltage will result in an increase of the density of the free holes rather than an increase of the channel in space. In the picture the width of the channel is exaggerated. In reality it is only a monolayer thick.
To complete the story, in strong inversion we have the following distribution of space charge and free carriers:
|depletion: Cd =||-----------||accumulation: Ca = Cox|
|Cox + CW|
x: from oxide to surface of film
y: from source to drain
z: along an electrode
Z: electrode width
Under the assumption that all the free carriers come from charges
the strong accumulation or depletion zone, it is very easy to
the amount of charge on the semiconductor side and hence the
the section above we have seen that the capacitance of an MIS
under these conditions is equal to the oxide capcitance, Cox.
Assuming no other capacitances, all the charges go to the
therefore, since C = Q/V we find Q
Cox VG. As written
we need VT to bring it into strong accumulation
therefore Q = Cox
With this in mind, and with the idea that the conduction is
to the charge as seen in equation I the current in the linear
IDS = Cox (VG -VT) mVDS Z/L
Remember that we arrived at this by the assumption that all the
carriers are located in the strong inversion or accumulation zone
to the interface and that the rest of the device is not
in materials with bulk Fermi levels close to the band edges, the
conductivity (the "off current") can be very large. In principle,
the material, the closer the Fermi level will be to mid gap and
off-current we will have. Making the films thinner also helps.
Moreover, not all the charge induced by the gate is free charge. The above model is also known as the Charge Control Model. If we do include the background conduction in the bulk and the depletion and inversion zones, we have to add a term to the above equation, to arrive at the Schottky model, see Sze and Shur .
VT = (4qesyBNA)1/2 / Cox + 2yB
As an example: for NA = 1x1016 cm-3,
= 50 mF/m2,
= 2.5 eV (yB = 1.25 V), es
= 5.0e0 we get VT
= 11.9 V + 2.5 V = 14.4 V; since the first term in the equation
the oxide and the second term comes from the semiconductor we can
most of the external voltage (83%) is absorbed by the oxide
The Fermi level, of course, also depends on the acceptor concentration, so in total we get a complex dependence on NA. In textbooks, it is assumed that all acceptors are ionized. In fact, for organic materials, where the acceptor level can be very deep (but abundant) this is not necessarily the case. In fact, we should read NA as "ionized levels" and this can be a fraction of the real number of acceptors, unlike in classical materials such as Si and GaAs. Moreover, the fraction of levels ionized can be changed by changing the band bending (by applying a gate voltage) and thus, the threshold voltage can change when putting the device in operation. Depending on the depth of the levels, these changes can be in the order of seconds, to minutes and hours and even days.
Note that high levels of current have no effect on this trapping of charges, since they do not attribute to a different band bending or extra charges in the interface.
Note that for an accumulation type FET this calculation does not work because we do not have a space-charge region caused by ionized acceptor levels; VT does then not depend on NA., but only on the Fermi level and the number of valence band states.
Remark: We have considered here an FET without a wire connected to the bulk of the device. If we do so, the threshold voltage reduces to VT = (2qes(yB-Vsub)NA)1/2 / Cox + 2yB, with Vsub the voltage of the substrate.
If you do the calculation correct, you will see that the distance of the Fermi level depends linearly on the gate voltage and with a square-root on the acceptor density NA. Hence the current follows something like (Sze , Szur )
If we assume a linear voltage drop from source to drain from 0 to 10 V, we can exactly calculate where the channel closes, namely at 10% distance from the drain. We have to bear in mind, though, that a closed channel has less free carriers and thus has higher resistivity. The law of continuity tells us that the current at every place of the device must be equal. Therefore, since voltage drop is current times resistivity, the voltage drops much faster in a closed-channel region than in a open-channel region. Moreover, if we assume that the free-carrier density in the closed-channel region is much smaller than the open-channel region, the pinch-off region is very small.
The voltage of start of saturation is easy to calculate. At this voltage the gate-drain voltage is exactly equal to the threshold voltage. VG-VD = VT. Thus (VS = 0, VD = VDS)
onset of saturation: VDS = VG-VT
Beyond this voltage, the current is constant. We will have a region from the source to near the drain with a voltage drop of VG-VTand a very thin region close to the drain with the rest of the voltage drop of VDS. The length of the first region is nearly independent of the total external voltage. It therefore has a contant length and voltage drop, and the current through it is therefore independent of VDS. Again, continuity tells us that the current at every point is equal, therefore, the saturation current is independnet of VDS.
With this we can calculate the free carrier density Q(x)
and the voltage V(x) of every point in the channel
onset of saturation. Along the way we will also calculate the
is the current in saturation.
Imagine putting up a screen at a distance x from the source, peprpendicular to the source-drain direction, stretching as long as the electrode lengths (Z) and as high as the film thickness. We can calculate the current I through such a screen.
The current I at a crossection at a certain point x is equal to the free-charge density at that point Q(x), the carrier mobility m and the local field E(x) = dV(x)/dx:
I(x) = ZmQ(x) dV(x)/dx
Because of continuity, this current has to be constant along x and equal to the drain-source current IDS. The above equation then reduces to
dV(x) / dx = IDS/ZmQ(x) (eq.I)
The free-carrier density is a function of the local field VG-V(x), as seen before:
Q(x) = Cox[VG-V(x)-VT] (eq.II)
The solution to this system of diferential equations is easy (take the derivative of the second equation and put this in the first), to which we add the following boundary condition:
1a: the charge at the drain is zero: Q(L) = 0.
1b: The voltage at the drain is just enough to close the channel: V(L) = VG-VT.
soulution is then
Q(x) = [(2CoxIDS/Zm)(L-x)]1/2
V(x) = (VG-VT) - [(2IDS/mZCox)(L-x)]1/2
Using the next boundary condition
2a: The voltage at the source is 0: V(0) = 0
2b: The charge at the source is Q(0) = Cox (VG-VT)
we can calculate the current
IDS = (1/2)m(Z/L) Cox (VG-VT)2
which is the current at the onset of saturation and,
we have shown before, the current beyond this point is independent
this is the current in saturation (as long as VG
< VDS + VT).
The total amount of charge stored in the device in saturation can be found by integrating the equation for the charge distribution above and multiplying by the device width Z:
at saturation, VDS = VG-VT: Q = (2/3) Z (VG-VT) Cox
in the same way:
at VDS = 0 V : Q = Z (VG-VT) Cox
Note: when we increase the bias, charge is coming out of the device. We have to be careful in our IV measurements that we do not measure the current of these charges going into and coning out of the device. See the section on displacement current.
We can also use the same method to calculate the current before
Going back to the general solution of the system of differential
V(x) = (VG-VT) - [(2IDS/mZCox)(x0-x)]1/2
As boundary conditions we now take:
1: The voltage at the source is 0; the charge is Cox (VG-VT)
2: The voltage at the drain is V(L) = VDS
The result is
IDS = m(Z/L) Cox [(VG-VT)VDS - (1/2)VDS2]
For completeness sake and for later reference, here are the
and voltage curves for the different regimes, ranging from 1)
2) linear regime, 3) onset of saturation, 4) in saturation.
onset of SAT
| Vs = IdsRc
Vd = Vds - Ids Rc
Vgs = Vg-Vs
Ids = mCoxZ/L (Vgs -VT) (Vd -Vs )
||The organic FETs are of the accumulation p-channel
the accumulation operation there is no space charge region
ionized acceptors. All the space charge and band bending
must come from
intrinsic carriers - unbalanced holes-electrons which still
p>n - and carriers in the strong
The result will be that we will still have the equations
IDS = (1/2)m(Z/L) Cox (VG-VT)2
The threshold voltage now becomes (see Horowitz )
||The FETs are thin-film transistors.|
||Organic materials have a large sub-threshold voltage current. This also makes that the saturation currents become voltage dependent because the assumption that the size of the region where the voltage drops VG-VT is constant is no longer valid. In the discussion above it was assumed that when the device is in saturation, the rest of the voltage is absorbed in a very thin region. Such a strong field can be sustained becuase of the low carrier density. In organic FETs we have a situation where the free-carrier density below threshold is already substantial. The pinch-off region therefore has to be much larger and the rest of the voltage is then absorbed in a smaller region. This gives larger electric fields and larger currents. The currents still rise for increasing VDS.|
||The mobilities are so low, that the above
apply. For instance, we can have charge built-up at the
will limit the currents. In this case, the diffusion
the current will take over in importance. See p. 443 of Sze.
The assumption that the current is only depending on the electrical field is wrong. Instead of
I = qmenE
we will have
I = qmenE + qDn dn/dx
For low mobilities, the first term becomes small and the second dominating. Obviously, this becomes more important when we approach saturation because then we have the largest gradient in carrier concentrations, especially in the pinch-off region close to the drain (see the figures above).
For low-mobility materials it is therefore advisable to measure in the linear region.
||Charge injection. In the above discussion it is
the injection of carriers in the channel is not a limiting
classic n-type inversion-channel FET the source and drain
in fact, made of n-type silicon. This means that, by the
is created, the Fermi levels in the electrodes and in the
exactly lined up (by definition) and there is no barrier at
Moreover, where there is no Fermi level alignement (outside the channel) there is a pn-junction that will prohibit conduction through anything else but the channel. We only have to worry about the charges inside the channel.
In organic FETs the situation is different. When the p-channel is created, we still are not sure if we have Fermi level alignment between the gold electrodes and the p-channel. Maybe we have to overcome a Schottky barrier. This can be simulated by a diode in series with the FET. It implies that for low VDS the current is zero until VDS = Vbi.
The proposed structure is the one here on the left. This, however would never conduct (always one of the two diodes is closed). The best way to analyze this is with an MSM device (metal-semiconductor-metal, see p. 613 of Sze). The idea is that the depletion widths on opposite two Schottky barriers can start overlapping for certain voltages. When this happens, at VST, the currents rapidly rise and the barriers effectively disappear. The voltage at which the device opens is therefore NOT the built-in voltage of a diode, but rather the voltage at which breakdown occurs. See Fig. 40 on page 618 of Sze.
Of course, this is not really an MSM device, because we also have the gate. How does this relate to the FETs we are using?
Note: the units presented here are