Theory of Metal-Insulator-Semiconductor Field-Effect
wrote this in
2004, I tried to make theory pages for our research on organic
thin-film transistors (TFTs). At that time, I did, just
like everybody else, make the assumption that a thin-film
just like a thin MOS-FET. Any theory of a MOS-FET I assumed to be
directly applicable to a TFT. This, however, proved to be wrong.
Recently we developed a theory specially designed for thin-film
(organic and inorganic alike). Click here
(http://www.ualg.pt/fct/adeec/optoel/theory/tft/) if you
want to study TFT
instead of MOS-FETs. These pages now exclusively deal
with MOS-FETs. At this moment, these pages are no longer relevant
to our research, but I keep them because they might anyway be
interesting for some people.
(in case you already want to see the TFT model, look for the two
publications in Synthetic Metals 156, p.1305 and p.1316).
The idea is here to present the theory of
I will try to do this in a very simplified way, cutting away all the
However, I am well aware that in this way, I may oversimplify
should serve as an introduction to get a feeling for electronic
This guide does not substitute serious books like Sze and Shur,
can be found at the end of this document.
As we will see, the
can be well described by a MIS-diode with source and drain
in the plain of the active layer. Therefore, it is best to start
::: MIS junction.
::: Capacitance of an MIS junction
::: Field-Effect transistor (inversion channel)
Threshold voltage of an inversion-channel FET
Subthreshold region of an
Peter Stallinga, July 2007.
To understand how an FET (of the MOSFET type) works, we first have
to analyze what an MIS structure is.
In a simple approximation, a MOSFET is a planar device of
material whose free carrier concentration n, and hence it
(via g = men)
by the gate.
The first figure shows an energy diagram of an MIS device. The
consists of a metal and a semiconductor separated by an insulator.
we assume that the insulator is not conducting any current.
Standard textbooks start with an ideal MIS device, which means
the Fermi levels in the metal and the semiconductor are aligned
contact. In other words, the work functions of the metal and of
are equal, fm = c
that we have no band bending in the absence of external voltages.
the Schottky barrier, where charge was flowing from one side to
due to the misalignment of the Fermi levels. In the ideal MIS
such a flow of charge is not needed (which saves us the trouble of
how it can pass through the oxide :-)
||fm : the
How much it costs to take an electron from the top of the
in the metal to vacuum. The "workfunction" of the
semiconductor can be
defined as c + EC-EF.
fb : (not
it doesn't enter into the calculations): the barrier
height of the
as seen from the metal; the difference between the
"conduction band" of
the oxide and the Fermi level of the metal..
c : the electron
semiconductor. The energy it takes to take an electron
from the conduction
band to the vacuum level.
EG : energy gap of the
YB : the
midgap level to the Fermi level. This is approximately
equal to EG /2
EC : bottom of conduction band.
EV : top of valence band.
|The following strip explains what happens when we
voltage to the metal (gate). For that we use the legend as
on the right.
Note that the (horizontal) SCALE of the pictures is
in Schottky barriers, the depletion width depends on the
the depletion width is shown as constant.
When a small (positive) voltage is connected to the metal
holes are pushed out of the interface region and a band
on the other side of the insulator. This is the same
effect as seen in
a Schottky barrier. Free carriers (holes) flow out of the
and a depletion zone is formed. The uncompensated
acceptors cause an electric field and - via Poisson's
equation - a
bending of the bands.
Note that there is also a voltage drop in the oxide. In
the oxide no
charges can reside and hence the field is constant and the
is linear in space. The total voltage drop in the oxide
plus the band
is equal to the external voltage.
When the voltage is further increased, at the interface an
region is created. The semiconductor becomes here n-type,
c) Strong Inversion
For very strong bias, the Fermi level crosses the
conduction band close
to the interface. This is strong inversion. Free
a so-called "channel" next to the oxide. This channel is
The ample availability of states in the conduction band
further increases in the gate voltage will not extend this
region into space, but rather will increase the density
in the channels. The channel is always infinitesimally
of free carriers can easily cause a large voltage drop
only a thin layer is needed to "absorb" the external
Note that the depletion width (the white zone) and the
(light blue zone) are constant once the channel is formed.
Going in the other direction, a negative voltage at the
will attract some free holes to the interface. In this accumulation
region, an increased number of free holes is created,
although it is
yet dramatic; the interface is still high-ohmic.
e) Strong accumulation
For stronger negative voltages at the gate the Fermi level
below the valence band at the interface. A channel with
holes is created. This is called strong accummulation.
Again, as for the strong inversion case, further
increasing the voltage
will result in an increase of the density of the free
holes rather than
an increase of the channel in space. In the picture the
width of the
is exaggerated. In reality it is only a monolayer thick.
To complete the story, in strong inversion we have the
distribution of space charge and free carriers:
The MIS junction is an ideal device for studying interface states
levels using the same techniques as demonstrated for the Schottky
The advantage lies in the fact that there is no DC current which
obscure our measurements.
Capacitance of an MIS junction:
The device can consist of several regions in series, each with it's
capcitance. The capacitance of the metal and of any part of the
with free carriers is zero. For the other two parts of the device,
insulator and the depletion region we can calculate:
Cox = eox
CW = es
The total capacitance is caluclated by taking the serial sum of the
In acuumulation there is no depletion layer and in this case, the
capacitance reduces to Cox. Once a depletion zone
formed, the capacitance depends on the frequency. For low
the generation-recombination current causes a short circuit of the
capacitance and the capacitance reduces to Cox.
7 on p. 371 of Sze
or Fig. 4-3-5a on p. 348 of Shur .
For high frequencies, the depletion zone is not short circuited and
measured capacitance is a series capacitance of the oxide and the
width. The depletion width is constant once it is fully formed (see
above) and we will measure a constant capacitance.
Cox x CW
Ca = Cox
|Cox + CW
Field Effect Transistor (FET)
An FET is nothing more than an MIS device with electrodes connected
two lateral sides of the semiconductor. Imagine connecting an
above and one below the images above. The first one we will call the
the latter the drain.
x: from oxide to surface of film
y: from source to drain
z: along an electrode
Z: electrode width
L: electrode distance
d: oxide thickness
The total current through this device is then linearly
to the number of free carriers in the semiconductor. The other
are the mobility m, the external
field Ex: and the device dimensions Z and
with IDS the total current, m
the mobility of the carriers, Vy the external
(is equal to VDS), Z the width of an
the distance from source to drain, and |Q| the amount of
charge in a line perpendicular to the oxide surface (along
C/m2. This is equal to integrating the electron and hole
(ignoring the sign) from the edge of the oxide to infinity (or to
of the semiconductor film), see the figure with free carriers above.
In case we have substantial contributions from both electrons and
holes, and they have different mobilities, we have to replace the
|Q|m with (|Qp|mp
We will see that this can explain the linear region of an FET. To
the IV curves in the linear region, we only have to calculate the
of free carriers. For the saturation region the equations are a
different, as will be shown later.
As a first order we can say that we only have free carriers when we
in strong inversion or strong accumulation. As can be seen from the
of figures above, we need to supply a certain voltage to the gate to
either strong inversion or strong accumulation.This is the so-called
voltage VT. This doesn't mean that we don't have
carriers and conduction below this threshold voltage, but that the
beyond this voltage is much larger.
Under the assumption that all the free carriers come from charges
the strong accumulation or depletion zone, it is very easy to
the amount of charge on the semiconductor side and hence the
the section above we have seen that the capacitance of an MIS
under these conditions is equal to the oxide capcitance, Cox.
Assuming no other capacitances, all the charges go to the
therefore, since C = Q/V we find Q
Cox VG. As written
we need VT to bring it into strong accumulation
therefore Q = Cox
With this in mind, and with the idea that the conduction is
to the charge as seen in equation I the current in the linear
Examples of IV curves (IDS vs. VDS;
for different gate voltages and transfer curves (IDS
right) for different drain-source voltages. VT = 2 V.
Remember that we arrived at this by the assumption that all the
carriers are located in the strong inversion or accumulation zone
to the interface and that the rest of the device is not
in materials with bulk Fermi levels close to the band edges, the
conductivity (the "off current") can be very large. In principle,
the material, the closer the Fermi level will be to mid gap and
off-current we will have. Making the films thinner also helps.
Moreover, not all the charge induced by the gate is free charge.
above model is also known as the Charge Control Model. If we do
the background conduction in the bulk and the depletion and
we have to add a term to the above equation, to arrive at the
model, see Sze
and Shur .
Threshold voltage of an
Following the above discussion and the MIS strip of figures, it is
that the band bending cannot be larger than the bandgap before
accumulation or strong inversion occurs. In other words, at the
strong inversion, the band bending Vbb is exactly
to the difference between the conduction band and the Fermi level, (EC-EF)/q
in the bulk.The depletion width is then (see section on Schottky
The electrical field at the interface is the integral of the space
inside this depletion region: Emax = (qNA/es)W
= (qNA2Vbb / es)1/2.
Maxwell's equations tells us that, in the absence of any charge, the
displacement D (=eE) is
accross the interface. On the semiconductor side of the junction we
In the oxide we therefore have an electrical field of Eox
This field is constant inside the oxide because there are no net
there. We therefore have an extra voltage drop of DV
= doxEox = (dox/eox)(qesNA2Vbb)1/2
accross the oxide. The total external voltage then becomes (dox/eox)(qesNA2Vbb)1/2
+ Vbb = VT.. With Vbb
equal to (EC -EF)/q
VT = (dox/eox)[2qesNA(EC-EF)/q]1/2
Remember that Cox = eox/dox,
and, in normal cases, the Fermi level is very close to the valence
so that (EC-EF)/q
= EG/q which we can call 2yB.
With this in mind, the above equation becomes the following text
for an n-type inversion channel:
/ Cox + 2yB
As an example: for NA = 1x1016 cm-3,
= 50 mF/m2,
= 2.5 eV (yB = 1.25 V), es
= 5.0e0 we get VT
= 11.9 V + 2.5 V = 14.4 V; since the first term in the equation
the oxide and the second term comes from the semiconductor we can
most of the external voltage (83%) is absorbed by the oxide
The Fermi level, of course, also depends on the acceptor
so in total we get a complex dependence on NA.
it is assumed that all acceptors are ionized. In fact, for organic
where the acceptor level can be very deep (but abundant) this is
the case. In fact, we should read NA as
and this can be a fraction of the real number of acceptors, unlike
materials such as Si and GaAs. Moreover, the fraction of levels
can be changed by changing the band bending (by applying a gate
and thus, the threshold voltage can change when putting the device
Depending on the depth of the levels, these changes can be in the
of seconds, to minutes and hours and even days.
Note that high levels of current have no effect on this trapping
charges, since they do not attribute to a different band bending
charges in the interface.
Note that for an accumulation type FET this calculation does not
because we do not have a space-charge region caused by ionized
levels; VT does then not depend on NA.,
only on the Fermi level and the number of valence band states.
Remark: We have considered here an FET without a wire connected
bulk of the device. If we do so, the threshold voltage reduces to
/ Cox + 2yB,
the voltage of the substrate.
Subthreshold region of an
The subtreshold region is the region of gate voltages before the
is opened. The desnity of free carriers at the interface is
depending on the distance between the conduction band and the Fermi
When the channel is formed, the Fermi level remains fixed (resonant)
the edge of the conduction band. Further increases in voltage result
in a tiny shift of EF; only minute changes in EF
are needed to create free charges Cox(VG-VT).
In the subthreshold region the distance EF-EV
is determined by the gate voltage and the acceptor concentration in
bulk in the following way (very similar to the calculation of the
1) Poisson's equation tells us that the band bending in the
is equal to double-integral of the density of ionized acceptors: Vbb
= double-integral NA
2) This will tell us the field at the interface and hence
3) The field and voltage drop in the oxide and hence the
4) Total voltage drop in the device.
5) Reversing these calculations, if we know the total voltage
the device, we will also know the band bending in the semiconductor.
6) If we know the band bending in the semiconductor and we know the
initial distance between Fermi level and conduction band, we will
the position of the Fermi level at the interface.
7) If we know the position of the Fermi level at the interface, we
know the density of free carriers at the interface (Fermi-Dirac
which is more or less exponential)
If you do the calculation correct, you will see that the distance
the Fermi level depends linearly on the gate voltage and with a
on the acceptor density NA. Hence the current
something like (Sze ,
exp[VG / NA]
If we increase the drain-source voltage eventually we will go into
where the current becomes independent of the drain-source voltage It
very easy to understand why this should happen. Imagine an FET with
voltage of VT = 1 V. We will apply a gate voltage
beyond this value, let's say 10 V. The channel is therefore open.
drain-source voltages, both the drain and the source and hence the
bulk region of the device is at 0 V, or close to 0 V at all places.
the drain, the gate-drain voltage is 10 V and this is well beyond
voltage. Here we have a conducting channel. At the source (which is
at 0 V), the gate-source voltage is also 10 V and here the channel
open. Actually, at all places do we have a conductive channel.
Let us now set the drain voltage to 10 V. At the source we still
a gate-source voltage of 10 V and the band bending here will still
a channel. However, at the drain, the gate and the drain are at the
voltage; the gate-drain voltage is 0 V and this is below the
voltage for creating a conductive channel. The channel is closed
This we call pinch-off.
If we assume a linear voltage drop from source to drain from 0 to
V, we can exactly calculate where the channel closes, namely at
from the drain. We have to bear in mind, though, that a closed
has less free carriers and thus has higher resistivity. The law of
tells us that the current at every place of the device must be
since voltage drop is current times resistivity, the voltage drops
faster in a closed-channel region than in a open-channel region.
if we assume that the free-carrier density in the closed-channel
is much smaller than the open-channel region, the pinch-off region
The voltage of start of saturation is easy to calculate. At this
the gate-drain voltage is exactly equal to the threshold voltage.
= VT. Thus (VS = 0, VD
onset of saturation: VDS = VG-VT
Beyond this voltage, the current is constant. We will have a
from the source to near the drain with a voltage drop of VG-VTand
a very thin region close to the drain with the rest of the voltage
of VDS. The length of the first region is nearly independent of
external voltage. It therefore has a contant length and voltage
the current through it is therefore independent of
Again, continuity tells us that the current at every point is
the saturation current is independnet of VDS.
With this we can calculate the free carrier density Q(x)
and the voltage V(x) of every point in the channel
onset of saturation. Along the way we will also calculate the
is the current in saturation.
Imagine putting up a screen at a distance x from the
peprpendicular to the source-drain direction, stretching as long
electrode lengths (Z) and as high as the film thickness. We can
the current I through such a screen.
The current I at a crossection at a certain point x
equal to the free-charge density at that point Q(x),
carrier mobility m and the local field
I(x) = ZmQ(x)
Because of continuity, this current has to be constant along x
and equal to the drain-source current IDS. The
equation then reduces to
dV(x) / dx = IDS/ZmQ(x)
The free-carrier density is a function of the local field VG-V(x),
as seen before:
Q(x) = Cox[VG-V(x)-VT]
The solution to this system of diferential equations is easy (take
the derivative of the second equation and put this in the first),
we add the following boundary condition:
1a: the charge at the drain is zero: Q(L)
1b: The voltage at the drain is just enough to
the channel: V(L) = VG-VT.
soulution is then
Q(x) = [(2CoxIDS/Zm)(L-x)]1/2
V(x) = (VG-VT) - [(2IDS/mZCox)(L-x)]1/2
Using the next boundary condition
2a: The voltage at the source is 0: V(0)
2b: The charge at the source is Q(0)
we can calculate the current
= (1/2)m(Z/L) Cox
which is the current at the onset of saturation and,
we have shown before, the current beyond this point is independent
this is the current in saturation (as long as VG
< VDS + VT).
The total amount of charge stored in the device in saturation can
found by integrating the equation for the charge distribution
multiplying by the device width Z:
at saturation, VDS = VG-VT:
Q = (2/3) Z (VG-VT)
in the same way:
at VDS = 0 V
Q = Z (VG-VT)
Note: when we increase the bias, charge is coming out of the
We have to be careful in our IV measurements that we do not
current of these charges going into and coning out of the device.
section on displacement current.
We can also use the same method to calculate the current before
Going back to the general solution of the system of differential
V(x) = (VG-VT)
As boundary conditions we now take:
1: The voltage at the source is 0; the charge
2: The voltage at the drain is V(L)
The result is
which is equal to what we found for the linear region,
the term VDS2 which becomes important
when we approach saturation. When we susbtitute VDS
we get the equation for the linear region. When we substitute the
condition VDS = VG-VT
we reproduce exactly the equation for saturation currents.
Examples of IV curves (IDS vs. VDS;
for different gate voltages and transfer curves (IDS
right) for different drain-source voltages. VT = 2 V.
= m(Z/L) Cox
For completeness sake and for later reference, here are the
and voltage curves for the different regimes, ranging from 1)
2) linear regime, 3) onset of saturation, 4) in saturation.
VDS = 0 V
VDS < VG-VT
VDS = VG-VT
onset of SAT
VDS > VG-VT
For short channels we can expect the following:
Non saturating saturation currents. We assumed that the
drop along the channel is comprised of two parts, a gradual drop VG-VT
independent of VDS over nearly the entire channel
the last part [VDS-(VG-VT)]
completely absorbed by an infinitesimal small region. When the
becomes shorter, the last part takes relatively more space and we
assume anymore that the voltage drop VG-VT
occurs over a constant amount of space independent of VDS.
In fact, this region becomes ever smaller and the field will
increase, together with the currents. In other words, the current
saturation no longer independent of VDS. See Fig.
on p.478 of Sze.
We can easiliy explain this. At the source and the drain we have a
depletion region (a zone without free holes in an n-p-n inversion
FET). This zone will absorb the entire voltage drop VDS-(VG-VT).
these zones are thin compared to the bulk. It is easy to
the width of these depletion zones (see the section on Schottky
ys = [2es/qNA
yd = [2es/qNA
for the depletion width at the source and drain respectively. Note
that they also depend on the gate; once the channel has formed, the
width at the source disappears, but we still keep a depletion width
the drain which will absorp the excess VDS. Note
this "barrier" at the drain doesn't hinder the current, because it
the forward direction for "minority carriers" (electrons for npn
When this depletion width becomes comparable to the channel length
we can expect short-channel effects. This also depends on the
Non-zero subthreshold currents. Before threshold, we have
on either side of the semiconductor. The depletion width W
follows the standard calculations. When the channel length is
these depletion regions can start overlapping. This will cause that
currents increase. This is easy to see why. When a carrier is
by diffucsion over the first barrier, into the "channel", it
starts feeling the fields of the second barrier on the other side
pulled away to that electrode; it has a significant chance of making
to the other side. In fact, the diffusion (space-charge limited
will dominate and the currents will be of the form J = VDS2.
Threshold voltage shift.
Because trapping of charges takes places, the current continuously
drops. To compensate for this, a larger voltage has to be applied at
gate to keep the same amount of mobile charges in the channel.
In the text the following variables and constants were used:
- Scientific American, July 1995.
- Physics of semiconductor devices, S.M. Sze, 2nd
& sons, 1981, ISBN 0-471-05661-8
- Physics of semiconductor devices, M. Shur, Prentice
- The Electrical Characterization of Semiconductors :
and Electron States (Techniques of Physics, Vol 14) by P.
Orton, ASIN: 0125286279
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Technology. ed. P. Bernier, S. Lefrant and G. Bidan,
- Fabrication and characterization of electronic devices
H.L. Gomes, PhD thesis, University of Wales at Bangor, 1993.
- Electronic levels in MEH-PPV, ICEL-2
P. Stallinga, H.L. Gomes, H. Rost, A.B. Holmes, M.G. Harrison,
Friend. Accepted for publication in Synthetic Metals.
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in semiconductors, D.V. Lang, J. Appl. Phys. 45,
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device, S. Forero, P.H. Nguyen, W. Bruetting, M.
Chem. Phys. 1, 1769 (1999).
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for publication in Synthetic Metals (1999), and references
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University Press, New York (1998).
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Hall, Upper Saddle River (1997).
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M. Murgia, K. Müllen, Organic Electronics 3, 43
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H.L. Gomes, F. Biscarini, M. Murgia, J.Appl.Phys. (2004).
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G. Horowitz, R. Hajlaoui, D. Fichou, A. El Kassmi, J. Appl.
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M.C.J.M. Vissenberg, M. Matters, Phys. Rev. B 57, 12964
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molecules, J.H. Schön, Ch. Kloc, R.A. Laudise, and B.
Phys. Rev. B 58, 12952 (1998).
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H.L. Gomes, P. Stallinga, F. Dinelli, M. Murgia, F. Biscarini,
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- For the physical constants I relied on the very useful CERN
It has the following official reference: C. Caso et al.,
European Physical Journal C3 (1998) 1.
||area of the interface
||temperature scanning speed
or DC capacitance
||hole capture rate
||hole emission rate
||valence-band level and
||(metal) work function
||total space charge
||life time or decay time
||total band bending
||applied external voltage
||Fermi level depth in
relative to conduction band
||permittivity of vacuum
Note: the units presented here are
In reality often different units are
instance, energies are nearly always
given in eV
depletion widths in nm or Å
and impurity levels in cm-3
written and maintained by Peter Stallinga
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